Due to long development cycles (and short schedules!), firmware designers often struggle to generate modular intellecutal property (IP) that is reusable between applications. Modularity relies heavily upon parameterization which can be a difficult challenge in firmware design. Instead of a single IDE with an integrated compiler, parameters are scattered across HDL design files, modeling tools (MATLAB/Octave/Python), vendor tools (Vivado/Quartus/Libero), and simulation tools (QuestaSim/Cadence). The modification of these parameters must be synchronized when reusing IP.
Happy Friday indeed, everyone! Coinciding with today’s release of REDHAWK SDR 1.10, one of our own, Andrew Cormier, has put together a fantastic guide for the excellent integration options gained in this release. Check it out here or the menu above under REDHAWK.