ZCU102

Vivado

Disable CPU Idling on the ZCU111 When Using the Vivado ILA

For the ZCU111 and ZCU102 development boards (and possibly other Ultrascale development boards), Xilinx has configured by default to idle the ARM processor when using the Vivado Hardware Manager and Vivado ILA. The following steps detail how to add a

100G

FPGA Projects Spotlight

Geon Technologies is well-known for leading the industry in software-defined radio (SDR) frameworks like REDHAWK SDR. However, Geon’s growing portfolio of exciting FPGA projects deserve the spotlight too! This post gives you a recap of some of the FPGA projects

FINS

Frequency Estimator – Rapid FPGA Development with FINS

Geon has developed a Frequency Estimator IP which can perform FFTs of configurable bin size to estimate the frequency of an RF input. The IP achieves high precision while consuming few resources. Development and integration of the IP was accelerated

FPGA

Programmable and Persona Devices – Part 3

In our previous two posts, I showed how to setup projects for a Persona Device and Programmable Device. We then ran through a quick systems check of allocating and deallocating personas within a Node. This time we’ll look at setting

BSP

Zynq UltraScale+ in OpenCPI – ZCU102 and ZCU111

Introduction As a component-based framework for heterogeneous processing, OpenCPI may play a critical role in the future of FPGA development. Already supported on various Zynq platforms such as the Zedboard, Matchstiq-Z1 and Ettus E310, OpenCPI has proven an interesting and