Introduction

Geon has kicked off a design using Xilinx’s ZCU111 Evaluation Board along with the 100G Ethernet Subsystem IP core. In order to confirm our understanding of the IP core paired with the ZCU111’s Quad SPF28 cage, we have developed a ZCU111 test harness for the IP core.

100GE Test Harness

This test design configures the IP core in internal loopback mode and then generates simple ethernet packets to send through the 100G Ethernet Subsystem IP core. Those packets are then received by the IP core and handed off to a Vivado Integrated Logic Analyzer. This ILA allows for hardware-runtime verification of the received packets within Vivado’s Hardware Manager.

Results and Next Steps

We validated the functionality of this IP core on the ZCU111 and in doing so solidified our understanding of the interfaces to this 100G Ethernet Subsystem. These are of course just some initial steps to get us started before using this technology in a larger design. Next up will be OpenCPI device support for the 100G Ethernet Subsystem on the ZCU111….