Introduction
As a component-based framework for heterogeneous processing, OpenCPI may play a critical role in the future of FPGA development. Already supported on various Zynq platforms such as the Zedboard, Matchstiq-Z1 and Ettus E310, OpenCPI has proven an interesting and potentially groundbreaking tool for FPGA component and application portability, especially in the context of Digital Signal Processing. It serves as a layer of abstraction between HDL design and specific vendor tools and hardware. Furthermore, it enables modular design of applications with portions in both software and hardware. OpenCPI ultimately aims to reduce the development effort required to migrate designs across hardware platforms.
All of this being said, as FPGA technologies continue to advance there is significant effort required to evolve OpenCPI so it remains at the cutting edge. Support for the Zynq UltraScale+ is critical in this respect, and we decided it is time to get it done.
Geon’s Solution
OpenCPI on the Zynq UltraScale+ MPSoC/RFSoC
Geon has forked OpenCPI 1.4 and released version release_1.4_zynq_ultra that includes support for the Zynq UltraScale+: OpenCPI Release 1.4 – Zynq UltraScale+ Edition.
As useful test platforms for the Zynq UltraScale+ work, Xilinx’s ZCU102 and ZCU111 evaluation boards have been enabled as OpenCPI HDL Platforms for this Zynq UltraScale+ release. There is no peripheral device support or RF support for these boards within OpenCPI at this time, but they are usable as hardware accelerators. The Board Support Packages for the two Xilinx evaluation boards were placed in the OpenCPI ZCU1XX BSP Project.
Documentation for getting started with these boards in OpenCPI can be found here:
To enable OpenCPI cross-compilation for the Zynq MPSoC/RFSoC, an OpenCPI Software Platform was developed. Since this Software Platform is not strictly tied to these evaluation boards, it exists in its own OpenCPI Xilinx 18.2 Software Platform Project
Additional steps for Software Support
In order to enable software support for these boards within OpenCPI, some additional steps were taken. First, we needed a process for configuring and building bootable SD card images for ZCU102 and ZCU111. To accomplish this, Geon forked Xilinx’s meta-xilinx and meta-xilinx-tools Yocto layers and patched them to support the ZCU102 and ZCU111.
In order to generate an SD card that has the OpenCPI required files (such as binaries, applications, etc…), the meta-opencpi Yocto layer was created. This layer also includes contents to enable out-of-the-box use of Vivado Logic Analyzers on the ZCU102 and ZCU111.
Finally, to simplify the end-user’s Yocto experience, a Google repo manifest (opencpi-manifest) pulls in all Yocto layers required to build an OpenCPI SD card image.
Results
Hardware and Software Compilation for the ZCU102 and ZCU111
With this release of OpenCPI, users can build HDL workers for the ZCU102 or ZCU111, and can build RCC workers and ACI applications for the Xilinx 2018.2 Software Platform:
$ ocpidev build --hdl-platform zcu102 --rcc-platform xilinx18_2
...
Hardware+Software Applications Run on the ZCU102 and ZCU111
Applications containing combinations of HDL and RCC workers can be executed on these boards.
Simple Testbias Application
$ ocpirun testbias.xml
...
$ hexdump test.output | head
0000000 0304 0102 0305 0102 0306 0102 0307 0102
0000010 0308 0102 0309 0102 030a 0102 030b 0102
0000020 030c 0102 030d 0102 030e 0102 030f 0102
0000030 0310 0102 0311 0102 0312 0102 0313 0102
0000040 0314 0102 0315 0102 0316 0102 0317 0102
0000050 0318 0102 0319 0102 031a 0102 031b 0102
0000060 031c 0102 031d 0102 031e 0102 031f 0102
0000070 0320 0102 0321 0102 0322 0102 0323 0102
0000080 0324 0102 0325 0102 0326 0102 0327 0102
0000090 0328 0102 0329 0102 032a 0102 032b 0102
FSK Reference Application in File-Read-Write mode
$ ./target-xilinx18_2/FSK filerw
...
On success, this application outputs the Orioles bird
$ eog out_app_fsk_filerw.bin
Next Steps
Moving forward, Geon is working on adding support for the 100G Ethernet Subsystem on the ZCU111 within OpenCPI. At this stage we have an ILA-based test harness for the 100G Ethernet and are working to integrate this into OpenCPI device workers along with a UDP/IP packetizer.
